一种高精度的FPGA电路面积时序预测方法  

A high accuracy area and delay estimator for FPGA implementations

作　　者：王佳伟[1,2] 黄志洪[1] 高同强[1] 杨海钢[1,2] 

机构地区：[1]中国科学院电子学研究所可编程芯片与系统研究室,北京100190 [2]中国科学院大学,北京100049

出　　处：《国外电子测量技术》2017年第6期31-35,共5页Foreign Electronic Measurement Technology

基　　金：国家自然科学基金(61404140)项目资助

摘　　要：在FPGA上设计应用电路时,逻辑综合过程和物理综合过程需要反复进行多次,来满足面积时序约束。为了加速整个FPGA CAD流程,提出了一种在物理综合之前,使用前馈神经网络预测面积时序的方法。和FPGA布局布线工具VTR 7.0的实验结果相比,该神经网络预测面积平均相对误差(MRE)达到4.9%,预测时序平均相对误差(MRE)达到6.4%,和现有文献相比,具有预测时间早,预测精度高的特点。该预测模型将帮助用户缩短设计周期,在逻辑综合阶段更加全面探索设计空间,提高设计质量。The logic synthesis stage and physical synthesis stage will be repeated several times, when mapping the logic circuits to FPGA, to meet the area and timing constraints. In order to accelerate the traditional FPGA CAD flow, this paper presents a feed-forward neural network to predict the area and delay before the physical synthesis stage. Compared to the placement and routing results from VTR 7.0, the mean relative error（MRE） of the predicted area is 4.9%, and the mean relative error（MRE）of the predicted delay is 6.4%. This method works at early stage, but acquires a high accu- racy compared to the related work. The estimator will help the designer reduce the design cycle and be capable of fully exploring the design space during the logic synthesis stage, thus improving the whole design quality.

关 键 词：FPGA CAD 面积 时序 预测 前馈神经网络 

分 类 号：TN402[电子电信—微电子学与固体电子学]