基于PDSOI的锁相环电路单粒子瞬变敏感性研究  

Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process

作　　者：于猛[1,2,3] 曾传滨[2,3] 闫薇薇[2,3] 李博[2,3] 高林春[2,3] 罗家俊[2,3] 韩郑生[1,2,3] 

机构地区：[1]中国科学院大学,北京100029 [2]中国科学院微电子研究所,北京100029 [3]中国科学院硅器件技术重点实验室,北京100029

出　　处：《微电子学与计算机》2017年第8期76-81,共6页Microelectronics & Computer

基　　金：国家自然科学基金项目(61404161)

摘　　要：分析了一款基于0.35μm PDSOI工艺的锁相环(PLL)电路的抗单粒子瞬变(SET)能力,利用相位抖动为表征参数评估SET对PLL电路的影响与产生影响的可能性.电路级仿真采用优化过的SET注入模型,提高了仿真预测的准确程度.分析了PLL电路的SET敏感节点与敏感工作状态,仿真与激光测试表明,分频器(DIV)与输出低压正发射极耦合逻辑(LVPECL)是最敏感的电路模块,其内部节点的敏感性与节点分布和电路工作状态关系密切.最恶劣情况下相位抖动可达输出周期的一半左右,分析结果有助于抗SET加固设计.Single-event transients （SET） sensitivity of a Phase-Locked-Lops （PLL） based on 0. 35μm PDSOI process has been analyzed. By measuring the phase iitter of PLI-s output, the impacts of SET and their occurring possibility have been evaluated. An optimized SET injection model was used in circuit level simulation to improve the accuracy of simulation prediction. The SET sensitive nodes and operating condition of circuit are analyzed, and the results show that frequency divider （DIV） and output Low Voltage Positive Emitter-Couple Logic （LVPECL） are the most sensitive sub-circuits, whose SET sensitivities are close related to their working condition. In the worst case, phase jitter can be up to about half of the output cycle. Analysis results would be helpful to the design of radiation hardening.

关 键 词：单粒子瞬变 锁相环 辐射效应 相位抖动 

分 类 号：TN386.1[电子电信—物理电子学]