一种多核SoC中基于Cache机制的存储结构设计  

A Storage Structure Design Based on the Cache Mechanism in a Multi-core SoC

作　　者：张多利[1] 张宇 宋宇鲲[1] 汪健 

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《微电子学与计算机》2017年第10期26-31,共6页Microelectronics & Computer

摘　　要：本文针对一种面向高密度计算的异构多核SoC系统,提出了一种层次化的共享二级存储结构(L2-Cache),以缓解系统数据处理速度与外部存储间的速度差异.所设计的层次化存储结构提供对象数据缓存功能,利用计数替换策略,减少二级存储污染,提高有效数据命中率;在计算时间间隙实现数据准确预读取和L2-主存同步操作,增加有效存储带宽.最终测试结果表明,采用层次化存储结构的设计兼顾了不同访存比应用的数据访存特性,平均访存性能提高31.1%,不同规模的矩阵运算最高获得1.573的加速比,整体任务计算时间平均减少了27.8%.A hierarchical shared secondary storage （L2-Cache） structure for a heterogeneous multi-core SoC face to high density calculation is proposed in this paper to ease the speed difference between data processing and data storage. The hierarchical storage structure provides objeet data caching function and reduce the pollution of secondary storage using count replacement strategy to improve valid data hit rate. The structure can also increase the effective memory bandwidth by L2 - main memory synchronous operation and accurate prefetching in data computing interval time. Final test results show that, L2-Cache design can adapt for various data＇s feature of different applications. The new design increase the average fetch performance of about 31.10%, and gain 1. 573 speed ratio highest of different sizes of matrix,and reduce the average computing time of about 27. 8%.

关 键 词：CACHE 多核系统 数据预取 缓存替换 

分 类 号：TN402[电子电信—微电子学与固体电子学]