一种含BJT缓冲级的高性能运算放大器的设计  

Design of a High Performance Operational Amplifier with BJT Buffer

作　　者：薛晓磊 吴勃庆 XUE Xiao-Lei WU Bo-Qing(Xidian University, Xi＇an 710071 ,China)

机构地区：[1]西安电子科技大学,陕西西安710071

出　　处：《通信电源技术》2017年第4期161-162,共2页Telecom Power Technology

摘　　要：与普通两级差分运算放大器相比,折叠式共源共栅运放能够提供高增益、共模抑制比、电源抑制比,还能够提高带宽。基于0.35μm BCD工艺设计了一种折叠式共源共栅差分运放,要求电源电压为3.3 V^5.5 V,仿真结果表明,该电路在3.3 V电源下,各指标都满足了设计要求。Compared with the ordinary two-stage differential operational amplifier,folding cascode cascade can provide high gain,common mode rejection ratio,power supply rejection ratio,but also can improve the bandwidth.Based on the0.35μm BCD process,a cascaded cascade differential op amp is designed,and the power supply voltage is 3.3 V^5.5 V.The simulation results show that the parameters meet the design requirements under the 3.3 V power supply.

关 键 词：折叠式共源共栅 运算放大器 BCD工艺 

分 类 号：TN722.77[电子电信—电路与系统]