基于FPGA的脉冲神经网络加速器设计  

A FPGA Based Spiking Neuron Network Accelerator

作　　者：沈阳靖 沈君成 叶俊[3] 马琪[1] 

机构地区：[1]杭州电子科技大学微电子CAD研究所,浙江杭州310018 [2]浙江大学超大规模集成电路研究所,浙江杭州310007 [3]杭州士兰微电子股份有限公司,浙江杭州310007

出　　处：《电子科技》2017年第10期89-92,96,共5页Electronic Science and Technology

基　　金：国家自然科学青年基金(61404041)

摘　　要：脉冲神经网络是一种基于离散神经脉冲原理进行信息处理的人工神经网络,文中提出了一种基于FPGA的灵活可配的脉冲神经网络加速器架构,能够支持神经网络拓扑结构、连接权值的灵活配置。该设计首先在算法层对LIF神经元模型进行公式分解和浮点转定点两个层次的优化,并在硬件实现中采用时分复用技术将硬件中实现的8个物理神经元复用为256个逻辑神经元。神经元模电压计算采用三级流水线架构,以提高神经元数据处理效率。通过采用Xilinx XC6SLX45 FPGA实现整个神经网络加速器,工作频率可达50 MHz,并基于该加速器构建手写数字识别网络架构,实验结果表明,采用MNIST数据集作为测试样例,该网络架构准确率可达93%。Spiking neural network is a kind of biologically-inspired neural networks that perform information processing based on discrete-time spikes. This paper proposes a FPGA based hardware accelerator,which supports the flexible configuration of topology and synapse weights. First,LIF（Leaky Integrate-and-Fire,LIF） model is optimized for hardware implementation,and then 8 physical LIF neurons are implemented,which could be extended to 256 neurons by using time-multiplexing technology. To improve the data processing efficiency of the spiking neuron,the design adopts three-stage pipeline architecture to calculate the neuron voltage. At last,the design is implemented on XC6SLX45 FPGA running over 50 MHz operation frequency. MINST database is used as an application example to demonstrate the configurability and efficiency of the proposed implementation. The experimental results show the accuracy of handwritten number classification could be achieved as high as 93%.

关 键 词：脉冲神经网络 LIF模型 时分复用 分类 

分 类 号：TN912.11[电子电信—通信与信息系统] TP183[电子电信—信息与通信工程]