基于异步NoC机制的Booth乘法器设计  

Booth Multiplier Based on Asynchronous NoC Mechanism

作　　者：冯广博 何安平[1,2] 吴尽昭[1] 冯志华 FENG Guang-bo;HE An-ping;WU Jin-zhao;FENG Zhi-hua(Guangxi Key Laboratory of Hybrid Computation and IC Design Analysis, Guangxi University forNationalities, Nanning 530000 ,China;School of Information Science and Engineering ,Lanzhou University ,Lanzhou 730000 ,China;Beijing Institute of Computer Technology and Application ,Beijing 100000,China)

机构地区：[1]广西民族大学广西混杂计算与集成电路设计分析重点实验室,南宁530000 [2]兰州大学信息科学与工程学院,兰州730000 [3]北京计算机技术及应用研究所,北京100000

出　　处：《内蒙古大学学报（自然科学版）》2017年第6期703-710,共8页Journal of Inner Mongolia University：Natural Science Edition

基　　金：国家自然科学基金(11371003;11461006;61402121);广西民族大学校级一般项目(2016YB029);广西民族大学研究生教育创新计划项目;广西民族大学相思湖青年学者创新团队资助

摘　　要：随着信息化社会的深入发展,数字集成电路技术运用得越来越广泛.乘法器是数字电路系统最重要的算术运算单元之一,影响了整个电路系统的工作效率.实际设计通常采用Booth结构作为数字乘法器实现框架,决定此类乘法器运算效率的最为关键的两个方面是:部分积产生和部分积合并.提出了一种从结构上采用独立路由寻址的机制来实现部分积的产生,设计方法上采用异步微流水线,控制机制上采取数据通路的方法,来设计基于异步NoC(Network On Chip)机制的Booth乘法器设计.最后,通过FPGA开发板进行了仿真和实现,并与传统的Booth乘法器性能做了对比分析.As the continuous development of social informationization,the digital integrated circuit technology was used more and more widely.The multiplier is one of the most important arithmetic units in a digital circuit system,and affects the efficiency of the whole system.The multiplier design usually uses the Booth structure as a digital multiplier implementation framework.Producing and merging partial products are the two aspects to determine the efficiency of the multiplier operation mostly.Based on asynchronous NoC（network on chip）mechanism,a Booth multiplier with an independent routing address to produce partial product and an asynchronous micro-pipeline for control is proposed.Simulation and implementation of the proposed method were performed on the FPGA development board,and performance difference between this method and the traditional one is compared.

关 键 词：片上路由 异步微流水线 BOOTH算法 乘法器 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]