一种低电压超低功耗动态锁存比较器  

A Low Voltage Ultra Low Power Dynamic Latched Comparator

作　　者：张章[1] 丁婧 金永亮 解光军[1] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009

出　　处：《微电子学》2017年第6期756-759,764,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404043;61674049;61401137);安徽省科技重大专项项目(16030901007);安徽省科技攻关项目(1501021037);中科院重点实验室开放课题(IIMDKFJJ-13-06;IIMDKFJJ-14-03)

摘　　要：提出了一种低电压超低功耗动态锁存比较器。采用了自适应双重衬底偏压技术,在适当时间将比较器进行顺向衬底偏压与零衬底偏压的切换,以取得功耗延时积(PDP)的优势最大化。为解决比较器不工作时静态功耗较大的问题,提出了一种关断结构。该比较器基于SMIC 180nm CMOS工艺,在400mV电源电压下进行了前仿真。前仿真结果表明,电路的平均功耗、响应时间、功耗延时积均显著下降。在时钟频率为14.7 MHz时,响应时间为34ns,功耗为123nW。A low voltage and ultra low power dynamic latched CMOS comparator was proposed.The selfadaptive double body biasing technique was used.The working process of comparator could be switched between the forward body biasing and the zero body biasing at the proper time.So the circuit＇s power delay product（PDP）had been optimized.In addition,in order to solve the problem that the static power consumption of the comparator was too large at idle time,a shutdown structure was proposed.It was designed and pre-simulated in SMIC 180 nm CMOS process with a supply voltage of 400 mV.The pre-simulation results showed that the average power dissipation,response time and PDP were significantly reduced.For the clock frequency of 14.7 MHz,the response time was 34 ns and the power consumption was 123 nW.

关 键 词：比较器 衬底偏压技术 低电压 阈值电压 

分 类 号：TN432[电子电信—微电子学与固体电子学]