基于RNS算法的高阶FIR滤波器设计  

Design of High Order FIR Filter Based on RNS Algorithm

作　　者：王巍[1] 李双巧 徐媛媛 杨正琳[1] 袁军[1] 王冠宇[1] 何雍春 

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《微电子学》2017年第6期788-792,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404019)

摘　　要：以{2~n-1,2~n,2~n+1,2^(n-1)-1,2^(n+1)-1}为余数基,在余数系统(RNS)的基础上设计了一种128抽头有限脉冲响应(FIR)滤波器。针对大位宽输入,利用基于华莱士(Wallace)树结构的纯组合逻辑电路,实现了二进制到余数的转换。相较于一般抽头中乘法器级联加法器的结构,设计的乘累加(MAC)单元将加法运算合并到部分积求和中,减少了一级模加法器,使得电路延时进一步减少。此外,通过对进位保留加法器(CSA)的中间结果取模,避免了加法运算引起的位宽增加,从而降低了整个运算的复杂度。电路在FPGA上设计实现。实验结果表明,该滤波器的延时为3.55ns,功耗为2 585mW,消耗的硬件资源明显降低。A 128-tap finite impulse response（FIR）filter based on residue number system（RNS）was designed.The moduli set{2^n-1,2^n,2^n＋1,2^（n-1）-1,2^（n＋1）-1}was adopted.The binary-to-residue conversion of wide bit width input was realized by the pure combinational logic circuit based on the Wallace tree structure.Compared with the general tapped structure in which the multiplier was cascaded with the adder,the proposed multiply-accumulate（MAC）unit＇s addition operation was combined into the partial product summation,and one level of the modular adders could be reduced.So the delay of the FIR could be further reduced.In addition,by keeping the residue form of middle results of the carry-save adder（CSA）,the expanding of bit width due to the addition operation was avoided.So the complexity of the whole operations was reduced.The proposed circuit was implemented with FPGA.The experimental results showed that the delay of the filter was 3.55 ns,and the power consumption was 2 585 mW.It consumed less hardware resource.

关 键 词：FIR滤波器 余数系统 前向转换 乘累加单元 

分 类 号：TN713[电子电信—电路与系统]