Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme  

作　　者：Jingyu ZHANG Minyi GUO Chentao WU Yuanyi CHEN 

机构地区：[1]Department of Computer Science and Engineering, Shanghai Jiao Tong University

出　　处：《Science China(Information Sciences)》2018年第1期132-145,共14页中国科学（信息科学）（英文版）

基　　金：supported by National Basic Research Program of China (973 Program) (Grant No. 2015CB352403);National Natural Science Foundation of China (Grant Nos. 61261160502, 61272099, 61303012, 61572323, 61628208);Scientific Innovation Act of STCSM (Grant No. 13511504200);EU FP7 CLIMBER Project (Grant No. PIRSES-GA-2012-318939);CCF-Tencent Open Fund

摘　　要：With the emerging of 3 D-stacking technology, the dynamic random-access memory（DRAM）can be stacked on chips to architect the DRAM last level cache（LLC）. Compared with static randomaccess memory（SRAM）, DRAM is larger but slower. In the existing research papers, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together, ranging from SRAM structure improvement, to optimizing cache tag and data access. Instead, little attention has been paid to designing an LLC scheduling scheme for multi-programmed workloads with different memory footprints. Motivated by this, we propose a self-adaptive LLC scheduling scheme, which allows us to utilize SRAM and 3 D-stacked DRAM efficiently, achieving better workload performance. This scheduling scheme employs（1） an evaluation unit, which is used to probe and evaluate the cache information during the process of programs being executed; and（2） an implementation unit, which is used to self-adaptively choose SRAM or DRAM. To make the scheduling scheme work correctly, we develop a data migration policy. We conduct extensive experiments to evaluate the performance of our proposed scheme. Experimental results show that our method can improve the multi-programmed workload performance by up to 30% compared with the state-of-the-art methods.With the emerging of 3 D-stacking technology, the dynamic random-access memory（DRAM）can be stacked on chips to architect the DRAM last level cache（LLC）. Compared with static randomaccess memory（SRAM）, DRAM is larger but slower. In the existing research papers, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together, ranging from SRAM structure improvement, to optimizing cache tag and data access. Instead, little attention has been paid to designing an LLC scheduling scheme for multi-programmed workloads with different memory footprints. Motivated by this, we propose a self-adaptive LLC scheduling scheme, which allows us to utilize SRAM and 3 D-stacked DRAM efficiently, achieving better workload performance. This scheduling scheme employs（1） an evaluation unit, which is used to probe and evaluate the cache information during the process of programs being executed; and（2） an implementation unit, which is used to self-adaptively choose SRAM or DRAM. To make the scheduling scheme work correctly, we develop a data migration policy. We conduct extensive experiments to evaluate the performance of our proposed scheme. Experimental results show that our method can improve the multi-programmed workload performance by up to 30% compared with the state-of-the-art methods.

关 键 词：3D-stacking technology cache architecture cache scheduling multi-programmed workloads memory system performance optimization 

分 类 号：TP4[自动化与计算机技术]