一种高电源抑制比无片外电容LDO设计  

Design of a high PSR output-capacitor-less LDO

作　　者：张伟[1] 袁圣越[1] 田彤[1] 

机构地区：[1]中国科学院上海微系统与信息技术研究所,上海200050

出　　处：《电子设计工程》2018年第3期93-97,共5页Electronic Design Engineering

摘　　要：设计了一种可用于射频前端芯片供电的高电源抑制比(PSR)无片外电容CMOS低压差线性稳压器(LDO)。基于对全频段电源抑制比的详细分析,提出了一种PSR增强电路模块,使100 kHz和1MHz处的PSR分别提高了40 dB和30 dB;加入串联RC补偿网络,保证了电路的稳定性;在LDO输出至误差放大器输入的反馈回路引入低通滤波模块,降低了由于输出端接不同负载对反馈回路的影响。电路采用UMC 65 nm RF CMOS工艺进行设计和仿真,整个芯片面积为0.028 mm2,仿真结果表明,本文设计的LDO的相位裕度为86.8°,在100 kHz处,PSR为-84.4 dB,输出噪声为8.3n V/Hz,在1 MHz处,PSRR为-50.6 dB,输出噪声为6.9 nV Hz,适合为噪声敏感的射频电路供电。A high power supply rejection(PSR)output-capacitor-less CMOS low drop-out regulator(LDO)was designed for RF front-end chip.Based on the analysis of the PSR in all frequency,a PSR enhancement circuit block was proposed,and the PSR increases 40 dB at 100 kHz and 30 dB at 1 MHz respectively.A series RC compensation network was introduced to assure the circuit stability.A low pass filter was added in the feedback path,which weakened the influence of the output noise on the feedback.The proposed LDO circuit was designed and simulated in UMC 65 nm RF CMOS process.The entire chip area was 0.028 mm^2.Simulation results showed that the phase margin of the proposed LDO was 86.8°,At 100 kHz,the PSR was-84.4 dB,and the output noise was 8.3 n V/Hz.At 1 MHz,the PSR was -50.6 dB,and the output noise was 6.9 nV/Hz,which was suitable to supply power for the noise-sensitive RF circuits.

关 键 词：微电子学 低压差线性稳压器 高电源抑制比 无片外电容 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]