LV/HV P-Well BiCMOS[B]芯片与制程结构  

Structure of LV/HV P-Well BiCMOS[B] Chip and Process

作　　者：潘桂忠 

机构地区：[1]上海贝岭股份有限公司,上海200233 [2]中国航天电子技术研究院第七七一研究所,陕西710600

出　　处：《集成电路应用》2018年第2期44-48,共5页Application of IC

基　　金：上海市软件和集成电路产业发展专项基金(2009.090027)

摘　　要：LV/HV P-Well BiCMOS[B]技术能够实现低压5V与高压100~700V(或更高)兼容的BiCMOS工艺。为了便于高低压MOS器件兼容集成,采用具有漂移区的偏置栅结构的HV MOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到高电压。采用MOS集成电路芯片结构设计、工艺与制造技术,依该技术得到了芯片制程结构。LV/HV P-Well Bi CMOS[B] technology can achieve Bi CMOS technology compatible with low voltage 5 V and high voltage 100 to 700 V(or higher). In order to facilitate the compatibility and integration of high and low voltage MOS devices, a HV MOS device with bias grid structure with drift region is used. High voltage can be obtained by changing the length, width, depth, and doping concentration of the drift region. Using MOS integrated circuit chip structure design, technology and manufacturing technology, the chip process structure is obtained by this technology.

关 键 词：集成电路制造 偏置栅结构 LV/HVP-WellBiCMOS[B]芯片结构 制程剖面结构 

分 类 号：TN405[电子电信—微电子学与固体电子学]