55 nm低功耗产品漏电流优化的机理研究及解决方案  

Research and Solution of Optimization in Leakage Current of 55 nm Low Power Products

作　　者：吴智勇 

机构地区：[1]上海华力微电子有限公司,上海201203

出　　处：《集成电路应用》2018年第2期49-51,共3页Application of IC

基　　金：上海市软件和集成电路产业发展专项基金(2015.150204)

摘　　要：半导体技术随着摩尔定律,工艺尺寸逐渐缩小,浅沟槽形貌对增加低功耗产品器件间的隔离效果,降低漏电流的作用越来越敏感^([1])。提出一种全新的优化浅沟槽形貌,降低器件间漏电流的设计理念^([2])及实现方法。通过软件设计并模拟不同浅沟槽形貌下,漏电流的表现,得到顶部形貌的曲率半径对漏电流有敏感表现的结论,为降低漏电流提供指导性思想^([3])。后续把理论模型运用到实际工艺的优化中,菜单中在硬掩模层刻蚀步骤结束及有源区开始刻蚀前,使用高能量、高压力及大流量的重聚合物气体,形成圆滑的顶部形貌。Semiconductor technology with Moore＇s law, the process size narrow, that to Improve STI profile low power device isolation effect, the effect of reduce leakage current is more and more sensitive. This article propose design idea that a new method will been used improve STI profile and reduce leakage current of device. Under different shallow groove shape through the software simulation, the performance of the leakage current, Device top profile of radius of curvature is sensitive for leakage current performance that provide guiding idea to reduce leakage current. Theoretical model is applied to the actual process of optimization. The high polymer gas of high implant、high pressure and mass flow be used to recipe of HM etch step stop and AA step etch.At the same time, the paper has also established the critical etching process to etch rate as a means of monitoring methods, to a good foundation for production stability.

关 键 词：集成电路制造 浅沟槽刻蚀 硬掩膜 工作区 漏电流 POLYMER 聚合物 

分 类 号：TN405[电子电信—微电子学与固体电子学]