一款BD2/GPS双模导航芯片SoC子系统设计方案  

SoC Subsystem in BD2/GPS Dual Mode Navigation Chip

作　　者：林广栋[1] 马宏星[1] 朱家兵[1] 陈金忠 

机构地区：[1]中国电子科技集团公司第三十八研究所,合肥230088

出　　处：《单片机与嵌入式系统应用》2018年第3期59-63,共5页Microcontrollers & Embedded Systems

摘　　要：介绍了一款北斗/GPS双模导航芯片中SoC子系统的设计方案。该子系统包括晶心公司设计的N10处理器、FPU协处理器,还包括UART、I2 C、SPI、GPIO等基本外设。该SoC子系统承载着软件的运行,并实现了处理器与外界的通信能力。根据上层软件的需求,该SoC子系统没有例化内存管理单元、缓存、外部中断管理单元等模块。该SoC子系统分别例化了程序和数据SRAM,可以使处理器更快速地进行取指与访存。这些设计决策简化了该SoC子系统的设计,同时提高了处理器的运行速度,降低了芯片的功耗和面积。A SoC subsystem in a BD2/GPS dual mode navigation chip is introduced.The SoC subsystem includes N10 CPU designed by Andes corporation,FPU coprocessor.It also includes basic peripherals such as UART,I2 C,SPI,GPIO.The SoC carries the software,and it realizes communication of the processor and the outside world.According to the complexity of software,the SoC subsystem has no instantiate MMU,Cache and other unnecessary modules.The SoC subsystem instantiates the local instruction and the data SRAM separately,which enables CPU fetch instruction and load/store data faster.The design simplifies the structure of the SoC,improves the CPU's performance,and reduces the power consumption and the area of the chip.

关 键 词：导航 SOC N10 北斗 GPS 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]