基于SerDes系统芯片边界扫描测试设计与电路实现  

BS design and circuit implementation for SoC based on SerDes

作　　者：代鸣扬 蔡志匡[1] 陈冬明 郭宇锋[1] 

机构地区：[1]南京邮电大学电子与光学工程学院射频集成与微组装技术国家地方联合工程实验室,江苏南京210023

出　　处：《南京邮电大学学报（自然科学版）》2018年第1期91-97,共7页Journal of Nanjing University of Posts and Telecommunications：Natural Science Edition

基　　金：国家自然科学基金(61504065;61574081);江苏省自然科学基金(BK20150848)资助项目

摘　　要：基于IP的So C设计能够有效提高设计效率,降低成本,是当前超大规模集成电路设计的主流解决方案。Ser Des作为一种复杂数模混合IP,可实现高速数据的接收与发送。文中针对So C芯片中Ser Des的PAD测试问题,提供两种改进的边界扫描测试技术,包括利用Ser Des自带的边界扫描测试电路将多个Ser Des进行串行测试,以及将Ser Des定义为一个PAD连接到顶层边界扫描链进行集成测试。文中基于SMIC 40 nm工艺,在一款自主设计的多核So C芯片中,应用Synopsys公司BSD Compiler工具实现了上述技术的电路设计,网表级仿真结果证明该方案的可行性和有效性。The SoC design based on IP can effectively improve the design efficiency and reduce costs, thus it is a main solution for VLSI design. SerDes, as a complex digital-analog mixed IP, can achieve high-speed data recepting and transmitting. Two improved boundary scan testing techniques are pro- posed, including serial testing of using boundary scan test circuit and defining SerDes as a PAD connect- ed to the top boundary scan chain for integration testing. Based on the SMIC 40 nm process, the BS de- sign Compiler tool of the Synopsys Company is used to implement the circuit design of the above technolo- gy. Simulation results show that the scheme is feasible and effective.

关 键 词：SERDES 边界扫描测试 串行测试 集成测试 

分 类 号：TN47[电子电信—微电子学与固体电子学]