考虑NBTI效应的逻辑门退化延迟模型  

Aging Delay Model of Logic Gate Considering NBTI Effect

作　　者：郭海霞 王燕玲 李小进[1] 孙亚斌 石艳玲[1] 

机构地区：[1]华东师范大学电子工程系,上海200241

出　　处：《微电子学》2018年第1期98-102,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61574056;61204038);上海自然科学基金资助项目(14ZR1412000)

摘　　要：基于45nm PTM模型,采用Hspice对基本逻辑门进行了仿真,并使用Matlab对仿真数据进行了三维延迟曲面拟合。在这些仿真基础上,建立了关于输入信号翻转时间t_i、输出负载电容C_L、阈值电压变化量ΔV_(th)的传播延迟t_p和输出翻转时间to的计算模型。采用时延模型对基准测试电路ISCAS85-C17进行了计算,并将计算结果与Hspice仿真数据进行了对比。结果表明,在仿真范围(t_i=0~100ps,C_L=0~2fF,ΔV_(th)=0~50mV)内,该时延模型计算值与仿真数据的相对误差在±10%以内。该模型及其计算方法可适用于大规模数字IC的可靠性设计。The propagation delay of logic gate under the impact of NBTI had been thoroughly evaluated by Hspice,and then the 3 Dsurface fitting on the data obtained from the 45 nm PTM had been carried out in Matlab.Based on these simulations,the propagation delay（tp）and the output slew rate（to）had been explored to be a function of input signal slew rate（ti）,output load capacitance（CL）,and the shift in threshold voltage（ΔV（th））caused by the NBTI.The benchmark circuit（ISCAS85-C17）had been analyzed on the basis of 45 nm PTM and the proposed degradation model.The calculated data and the Hspice simulated data were compared.The results showed that the calculated error was less than±10%（@ti=0~100 ps,CL=0~2 fF,ΔV（th）=0~50 mV）compared with the simulated data.The proposed model and the calculation method could be embedded into the reliability design of large scale digital IC.

关 键 词：负偏压温度不稳定性 逻辑门 可靠性设计 门延迟模型 

分 类 号：TN432[电子电信—微电子学与固体电子学]