VLSI时钟布线算法的研究进展  

Progresses in the Research of VLSI Clock Routing Algorithms

作　　者：李海军[1] 严晓浪[1] 马琪[1] 

机构地区：[1]杭州电子工业学院,杭州310037

出　　处：《微电子学与计算机》2002年第8期53-56,共4页Microelectronics & Computer

摘　　要：随着集成电路工艺技术进入深亚微米、超深亚微米阶段,时钟频率已达到数GHz。设计一个高速、零偏差、低功耗的时钟布线算法已成为一项紧要的任务。文章简要介绍了时钟布线算法的研究进展,包括拓扑生成、实体嵌入、缓冲器插入和变线宽优化等各个阶段的各种算法,并指出了目前这些算法存在的一些问题。With the VLSI fabrication technolog y moving into deep sub -micron territory(DSM),clock frequency has reached several GHz.To design a high -speed,zero -skew and low -power clock routing algorithm has become a vital important and critical task.This paper briefly in troduces the progresses in the research of clock routing algorithm s,including algorithms of topology generation,embedding of a bstract topology,buffer inser-tion and wire sizing.The paper also p oints out some drawbacks of the present algorithms.

关 键 词：VLSI 时钟布线算法 零偏差 拓扑生成 实体嵌入 缓冲器插入 变线宽优化 超大规模集成电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]