芯片设计中CPPR问题的分析和解决  

Analyze and Resolve the Problem of CPPR in Chip Design

作　　者：楼久怀 宋勇 LOU Jiuhuai;SONG Yong(Shanghai Zhaoxin Semiconductor Co.,Ltd,Shanghai 201203,China.)

机构地区：[1]上海兆芯集成电路有限公司,上海201203

出　　处：《集成电路应用》2018年第5期11-14,共4页Application of IC

基　　金：工业和信息化部国家核高基(核心电子器件;高端通用芯片及基础软件产品)专项基金(2014ZX 01029101)

摘　　要：随着芯片制造工艺越来越先进,芯片中晶体管的偏差也会越来越大,所以时序分析的时候要考虑晶体管的制造差异,即OCV(on-chip variation)。在时序分析中,用set_timing_derate用来模拟芯片的OCV,如果设置timing derate,报timing的时候要考虑CPPR(Clock Path Pessimism Removal)。在Tempus中,用report_timing和report_cppr来报CPPR信息,这两个command报的CPPR值可能会不一样。这时,要根据项目设计要求,设command或者timing constraint来定义clock path的路径,计算正确的CPPR值。As the manufacturing process of chip is becoming more and more advanced, the deviation of transistors will be bigger, so we need to consider the difference of transistors in timing analyze, that is OCV（on-chip variation）. We use set_timing_derate to simulate the OCV of chip in timing analyze. If timing derate is set, CPPR（Clock Path Pessimism Removal） will be considered when report timing. In Tempus, we use report_timing and report_cppr to report CPPR, the results maybe different for these two commands. At this time, we need to set commands or timing constraints to define clock path according to the design requirement, and calculate the correct CPPR.

关 键 词：集成电路设计 芯片工艺偏差 CPPR(Clock PATH PESSIMISM Removal) 公共路径 时序收敛 分叉点 

分 类 号：TN402[电子电信—微电子学与固体电子学]