高速低功耗CMOS动态锁存比较器的设计  

Design of High-Speed Low-Power CMOS Dynamic Latched Comparator

作　　者：李靖坤[1,2] 杨骁 陈国晏[1,2] 娄付军 邱伟彬 LI Jingkun;YANG Xiao;CHEN Guoyan;LOU Fujun;QIU Weibin(College of Information Science and Engineering,IIuaqiao University,Xiamen 361021,China;Key Laboratory of ASIC and System of Xiamen,Xiamen 361008,China)

机构地区：[1]华侨大学信息科学与工程学院,福建厦门361021 [2]厦门市ASIC与系统重点实验室,福建厦门361008

出　　处：《华侨大学学报（自然科学版）》2018年第4期618-622,共5页Journal of Huaqiao University(Natural Science)

基　　金：福建省科技计划重点项目(2013H0029); 福建省泉州市科技计划项目(2013Z33); 华侨大学研究生科研创新能力培育计划资助项目(1511301027)

摘　　要：提出一种高速低功耗动态锁存比较器,电路包含预放大器、锁存比较器和SR锁存器3部分.采用一种新的锁存比较器复位电路,该电路仅由一个P沟道金属氧化物半导体(PMOS)管构成,实现电荷的再利用,减小了延迟,降低了功耗.SR锁存器输入端口的寄生电容为锁存比较器的负载电容,对SR锁存器的输入端口进行改进,避免由于锁存比较器的负载电容失配导致的输入失调电压偏移的问题.电路采用TSMC 0.18μm互补金属氧化物半导体(CMOS)工艺实现.结果表明:电源电压为1.8V,时钟频率为1GHz时,比较器精度达0.3mV;最大输入失调电压为8mV,功耗为0.2mW;该比较器具有电路简单易实现、功耗低的特点.A high-speed low-power dynamic latched comparator including apre-amplifier,a latched comparator and a SR-latch is presented.A novel reset circuit that only has one PMOS transistor is adopted for the latched comparator,which can realize the electric charge reusing.As a result,the delay and power consumption are reduced.The parasitic capacitance of input transistors of the SR-latch acts as the load capacitance of the latched comparator.An improved method for the SR-latch is adopted to avoid shifting of the input offset voltage caused by the load capacitance mismatch of the latched comparator.The comparator is implemented with TSMC 0.18μm complementary metal-oxide-semiconductor（CMOS）technology.Simulation results show that a sensitivity of 0.3 mV and a maximum input offset of 8 mV are achieved with the operating frequency of1 GHz,and the power consumption is 0.2 mW with 1.8 Vsupply.The dynamic latched comparator is concise and simple to implement,and has features of low power.

关 键 词：动态锁存比较器 互补金属氧化物半导体 高速低功耗 失调电压 

分 类 号：TN432[电子电信—微电子学与固体电子学]