众核处理器访存链路接口的FPGA验证  

FPGA verification for memory link interface of many-core processor

作　　者：周宏伟[1] 徐实 王忠奕 杨乾明[1] 冯权友[1] 邓让钰[1] 窦强[1] ZHOU Hongwei;XU Shi;WANG Zhongyi;YANG Qianming;FENG Quanyou;DENG Rangyu;DOU Qiang(College of Computer,National University of Defense Technology,Changsha 4100 73,China;College of Computer Science and Electronic Engineering,Hunan University,Changsha 410082,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]湖南大学信息科学与工程学院,湖南长沙410082

出　　处：《国防科技大学学报》2018年第3期176-182,共7页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(61303069;61472432;61602498);核高基重大专项基金资助项目(2015ZX01028101)

摘　　要：面向众核处理器提出一种访存链路接口的现场可编程门阵列(Field-Programmable Gate Array,FPGA)验证平台,用于对处理器访存链路关键部件进行功能及可靠性测试。提出片上读写激励自动产生与检查机制、以太网接口硬件用户数据报协议(User Datagram Protocol,UDP)协议栈和FPGA芯片间多通道并行链路三项关键技术并进行设计实现。实验结果表明提出的各项关键技术功能正确,不仅丰富了功能验证中随机激励产生及结果验证的手段,而且实现了对链路数据检错和多lane间延迟偏斜纠正逻辑的可靠性测试与评估。经过该平台验证的访存链路接口在实际芯片中通过了功能正确性测试,证明了验证的有效性。An FPGA（ field-programmable gate array） verification platform for memory link nterface of many-core processor was peoposed to test the function and reliability of the main components of the processor’s memory access link. Three key technologies, the on-chip read-writerequests automatic generation and result checking mechanism, the hardware UDP（user datagram protocol ） protocol stck in Ethe multi-lane parallel ink between FPGA chips were proposed and implemented. Experiments on the platform show that the proposed technologies are correct, they not only enrich the ways of the random request generation and result checking for functional verification, but also can test and evaluate the logics of link error detection and lane-to-lane deskew. The proposed platform has been used to verify a real many-core processor in which the function of memoty link interface is correct, so the validity of the verificaton is proved.

关 键 词：众核处理器 访存 链路 现场可编程门阵列 验证 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]