基于MOS电流模逻辑的4/5双模前置分频器设计  

The Design of 4/5 Dual-Modulus Prescaler Based on MCML

作　　者：朱艳霞 梁蓓[2] 杨发顺 ZHU Yanxia;LIANG Bei;YANG Fashun(School of Big Date and Information Engineering,Guizhou University,Guiyang 550025,China;School of Science and Technology,Guizhou University,Guiyang 550025,China)

机构地区：[1]贵州大学大数据与信息工程学院,贵州贵阳550025 [2]贵州大学科技学院,贵州贵阳550025

出　　处：《电子科技》2018年第5期69-72,共4页Electronic Science and Technology

基　　金：贵族省重大科技专项(黔科合重大专项字[2015]6006)

摘　　要：为满足高频通信的要求,文中设计了基于MOS电流模逻辑的4/5双模前置分频器。在分析MCML电路的工作原理的基础上,用已优化参数的MCML电路设计了逻辑或门与锁存器,并基于该或门与锁存器设计了4/5双模前置分频器。利用Cadence工具进行仿真,仿真结果表明,在采用SMIC 0.13μm CMOS工艺,电源电压为1.2 V,尾电流I_(ss)为50μA的条件下,该分频器最高工作频率可达到5 GHz。与同等条件下其他结构的电路相比,基于MOS电流模逻辑的4/5双模前置分频器的设计大大降低了功耗并提高了处理速度。This paper designed a 4/5 dual-modulus prescaler-based MOS current mode logic for high frequency telecommunication applications. Based on the analysis of MCML circuit working principles,logic OR gate and latch unit have been designed with parameters-optimized MCML circuit while 4/5 dual-modulus prescaler has been designed based on OR gate and latch unit above mentioned. This paper used Cadence as a simulation tool which adopted SMIC 0. 13 μm CMOS fabrication process. The simulation result showed that the maximum working frequency of this frequency divider is up to 5 GHz on the condition of 1. 2 V supply voltage and 50 μA tail current. The design of 4/5 dual-modulus prescaler-based MOS current mode logic dramatically decreased power consumption and improved the processing speed compared to other structured circuits on the same conditions.

关 键 词：MCML 或门 锁存器 主从D触发器 分频器 

分 类 号：TN772[电子电信—电路与系统]