Virtex-7 FPGA DDR3电路的设计与仿真研究  

Design and Simulation of Virtex-7 FPGA DDR3 Circuit

作　　者：孔维刚 陈长胜[1] 张旭[1] KONG Wei-gang;CHEN Chang-sheng;ZHANG Xu(Xi＇an Aeronautics Computing Technique Research Institute,AVIC,Xi＇an 710068,China)

机构地区：[1]航空工业西安航空计算技术研究所,陕西西安710068

出　　处：《航空计算技术》2018年第4期93-96,共4页Aeronautical Computing Technique

基　　金：国家重点基金项目资助(31511020102)

摘　　要：Virtex-7 FPGA属于高端高性能FPGA产品,在高速网络设备中得到了越来越广泛的应用,外接大容量高速DDR3存储是Virtex-7 FPGA电路设计需要解决的关键问题之一。介绍了Virtex-7 FPGA外接DDR3存储电路的设计方法,包括接口电路设计,时钟电路设计和供电电路设计。针对Virtex-7 FPGA对DDR3的拓扑及PCB布线设计要求,利用仿真工具Hyper Lynx进行了信号完整性仿真分析和验证,可以满足设计要求。Virtex-7 FPGA which belongs to high-end and high-performance FPGA is more and more widely used in high speed network equipments. The circuit design of large-capacity and high-speed DDR3 for Virtex-7 FPGA is one of the key technologies. This paper introduces the design circuit of DDR3 based on Virtex-7 FPGA,including interface circuit,clock circuit and power circuit. In order to realize the requirements of DDR3 topology and PCB layout for Virtex-7 FPGA,signal integrity simulation and validation is implemented by Hyper Lynx. The simulation results meet the design requirements.

关 键 词：VIRTEX-7 FPGA DDR3 拓扑 信号完整性 阻抗控制 

分 类 号：TN710[电子电信—电路与系统]