片间高速图像传输系统的设计与实现  

Design and Implementation of High Speed Inter-Chip Image Transmission System

作　　者：任强 姚远程[1,2] 秦明伟 REN Qiang;YAO Yuancheng;QIN Mingwei(School of Information Engineering,Southwest University of Science and Technology,Mianyang 621010,China;Robot Technology Used for Special Environment Key Laboratory of Sichuan Province,Mianyang 621010,China)

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010 [2]特殊环境机器人技术四川省重点实验室,四川绵阳621010

出　　处：《自动化仪表》2018年第9期34-39,共6页Process Automation Instrumentation

基　　金：国家重大科学仪器设备开发基金资助项目(2016YFF0104003)

摘　　要：针对图像采集与处理系统研发中的现场可编程门阵列(FPGA)之间的高速图像数据传输问题,设计了一种全双工、高吞吐率、高稳定性和高抗干扰能力的高速图像数据传输方案。设计的片间高速图像传输系统提供了通用的图像传输接口,可兼容不同的数据位宽和用户时钟频率。高速图像传输模块分为协议层和物理层。协议层包括跨时钟域电路和CXP图像传输协议编译码电路,完成跨时钟域和图像数据流编译码处理;物理层基于Aurora 8B/10B core,完成数据流的串并转换以及多通道绑定等处理,并采用GTH收发器实现高速串行数据的收发。仿真测试表明,图像数据传输正确,图像数据流同步时钟最高可达250 MHz,传输位宽达128 bit,最高吞吐率可达32 Gbit/s,平均吞吐率为20 Gbit/s,并且还有很大的提升潜力。该高速图像传输系统能够实现高吞吐率、高抗干扰、低错误率的图像数据传输,有助于各种不同视觉测量系统和图像处理系统的开发,具有广泛的应用价值。Aiming at the issue of high-speed image data transmission among field programmable gate array（ FPGA） chips in research and development of image acquisition and processing system; a full duplex high-speed image data transmission scheme with high throughput, high stability, and high anti-interference capability is designed. This inter-chip high-speed image transmission system provides a universal image transmission interface that is compatible with different data bit widths and user clock frequencies. The high-speed image transmission module is divided into a protocol layer and a physical layer. The protocol layer includes a cross-clock domain circuit and a CXP image transmission protocol encoding/decoding circuit to complete crossclock domain and encoding and decoding of image data stream; the physical layer based on the Aurora 8 B/10 B core completes the serial-parallel conversion of the data stream and multi-channel binding and other processing,and use GTH transceiver to achieve high-speed serial data receiving and sending. Simulation tests show that the image data transmission is correct,the image data flow synchronization clock is up to 250 MHz,the transmission bit width is up to 128 bit,the maximum throughput rate is up to32 Gbit/s,the average throughput rate is 20 Gbit/s,and a great potential for improvement still exists. The system can realize image data transmission with high throughput,high anti-interference,and low error rate,it is helpful for the development of various vision measurement systems and image processing systems,and has a wide range of application values.

关 键 词：图像处理系统 高速图像数据传输 AURORA 8B/10B CORE 串并转换 图像传输协议 收发器 高速串行 FPGA 

分 类 号：TH7[机械工程—仪器科学与技术] TP332[机械工程—精密仪器及机械]