一种新型电压电流混合加权12位DAC  

A New 12-bit Voltage-Current Mixed-Weighted DAC

作　　者：刘虹宏 陈隆章 高炜祺[1] 万辉[1] LIU Honghong;CHEN Longzhang;GAO Weiqi;WAN Hui(Sichuan Institute of Solid-State Circuits,China Electronics Technology Group Corp.,Chongqing 400060,P.R.China;Chongqing Southwest Integrated Circuit Design Co.,Ltd.,Chongqing 400132,19.R.China)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]重庆西南集成电路设计有限责任公司,重庆400132

出　　处：《微电子学》2018年第4期443-447,共5页Microelectronics

摘　　要：设计并实现了一种双路12位电压输出型数模转换器(DAC)。采用"10+2"分段式结构,高10位采用开关树电阻串DAC架构,保证了DAC良好的单调性。低2位采用电流舵DAC架构,从整体上减小了DAC的面积。12位DAC未经修调即可实现12位转换精度。该DAC采用0.35μm标准CMOS工艺实现,芯片尺寸为2.59mm×2.09mm。测试结果表明,在电源电压为5V时,DAC的功耗为19.5mW,DNL为-0.2LSB,INL为-2.2LSB,输出建立时间为2.5μs。在采样频率为480kS/s、输出频率为1kHz的条件下,DAC的SFDR为65dB。A dual 12-bit voltage output DAC with ＂10＋2＂segmented architecture was designed and implemented.The 10 MSBs adopted a structure of switch-tree resistor string DAC to ensure good monotonicity.The2 LSBs adopted a structure of current steering DAC,which reduced the area of DAC.The proposed architecture allowed the 12 bit DAC to achieve 12 bit of precision without trimming.The DAC was fabricated in a 0.35μm standard CMOS process,and the die area was 2.59 mm×2.09 mm.Tested results showed that the DAC consumed19.5 mW at a 5 Vsupply.The DAC had a DNL of-0.2 LSB and an INL of-2.2 LSB.The settling time was 2.5μs.The SFDR reached 65 dB when the sampling rate was 480 kS/s and the output rate was 1 kHz.

关 键 词：数模转换器 轨轨输出缓冲 内部基准 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792