一种多模LDPC译码器的可重构结构  

A Reconfigurable Structure in Multi-Mode LDPC Decoder

作　　者：唐中剑 王泽芳[1] TANG Zhongjian;WANG Zefang(Department of Information Engineering,Chongqing Youth Vocational ＆ Technical College,Chongqing 400712,P.R.China)

机构地区：[1]重庆青年职业技术学院信息工程系,重庆400712

出　　处：《微电子学》2018年第4期475-479,共5页Microelectronics

基　　金：重庆市教委科研项目(KJ1738463)

摘　　要：在分析低密度奇偶校验码(LDPC)算法的基础上,根据可重构思想,提出了一种支持12种模式LDPC的可重构结构。调用不同配置参数,重新组合译码器结构,实现可重构译码。利用接收到的移位配置信息,重构不同位宽的数据循环移位网络。采用NMS优化的TDMP算法,降低了系统硬件开销和系统级应用的复杂度,节省了芯片面积。该译码器基于TSMC 0.13μm CMOS工艺进行设计。结果表明,该译码器的最大时钟频率达240 MHz,最高吞吐率达1.568Gbit/s。相比于其他可重构结构的译码器,该译码器的芯片面积更小,支持的模式更多。Based on the analysis of LDPC decoding algorithms,a reconfigurable structure supporting 12 modes of LDPC decoding was proposed.The decoder structure could be recombined by invoking different configuration parameters,and the data cyclic shift network for different bit width could be reconfigured by shifting configuration information.With the TDMP algorithm optimized by NMS,the decoder could reduce the system hardware overhead,save the chip area,and lower the complexity of the system-level application.The decoder was designed in TSMC 0.13μm CMOS process.Simulation results showed that the maximum clock frequency of the proposed decoder was up to 240 MHz and the maximum throughput was up to 1.568 Gbit/s.Compared with other reconfigurable structure,the presented decoder had a smaller area and could support more modes.

关 键 词：低密度奇偶校验码 译码器 多模 可重构结构 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN734