一种千万门FPGA芯片中DSP硬核的设计  

Design of a DSP Hard IP of Ten-Million-Gate FPGA

作　　者：李正杰 张英 LI Zhengjie;ZHANG Ying(Chengdu Sino Microelectronic Technology Co.,Ltd.,Chengdu 610041,P.R.China)

机构地区：[1]成都华微电子科技有限公司,成都610041

出　　处：《微电子学》2018年第4期485-490,共6页Microelectronics

基　　金：国家十二五重大专项资助项目

摘　　要：提出了一种千万门FPGA芯片中DSP硬核的设计。基于SMIC 65nm CMOS工艺,以全定制技术设计实现了一个高性能的DSP硬核。DSP硬核主要包括输入输出逻辑、乘法器、XYZ选择器和模式控制单元、加法器等部分。为了提高DSP硬核的速度、面积和功耗等性能指标,采用了多种技术。通过2阶Booth编码设计,减小了50%的部分积数量;通过符号位扩展优化算法,大大减少了部分积符号扩展位,相应减少了逻辑资源和功耗;通过多种压缩器,减小了部分积加法路径上的延时,提高了乘法运算速度;通过超前进位加法器,提高了加法器运算速度。对DSP硬核进行仿真验证,并对千万门FPGA芯片进行测试。结果表明,该DSP硬核的功能和性能指标符合设计要求。A DSP hard IP of ten-million-gate FPGA was designed in SMIC 65 nm CMOS process.A high performance DSP hard IP was implemented by using a full custom design.DSP hard IP mainly includes input/output logic circuits,multipliers,XYZ multiplexers and mode control units,adders,etc.Some techniques were used in the DSP hard IP to improve the speed and to reduce the chip area and circuit’s consumption.For example,half number of the partial products was reduced by 2 nd order Booth encoder.The sign extend bit of partial products was decreased greatly by sign extend bit generation algorithm with logic resources and consumption curtailed accordingly.The delay of adding path of partial products was shortened by multi-types of compressors with the speed of multiplication accelerated.The operating speed of adder was expedited by the carry look-ahead adder.The DSP hard IP was simulated and verified.The chip of ten-million-gate FPGA was tested.The results showed that the function and performance of DSP hard IP met the design requirements.

关 键 词：FPGA DSP BOOTH编码 压缩器 超前进位 

分 类 号：TN432[电子电信—微电子学与固体电子学]