一款8位高速逐次比较型ADC的设计  

A 8-Bit High Speed Successive Approximation Analog-to-Digital Converter

作　　者：王堋钰 高博[1] 钱正[1] 龚敏[1] 谭萍 WANG Pengyu;GAO Bo;QIAN Zheng;GONG Min;TAN Ping(Sichuan Key Lab.of Microelectronics Technology,Division of Microelectronics,College of Physics Science and Technology,Sichuan University,Chengdu 610065,China)

机构地区：[1]微电子技术四川省重点实验室四川大学物理科学与技术学院微电子系,成都610065

出　　处：《电子与封装》2018年第9期15-19,共5页Electronics & Packaging

摘　　要：基于CSMC 180 nm CMOS工艺,设计了一款8位逐次逼近(SAR)A/D转换器芯片。采用了改进型的DAC结构,不仅解决了最高位电容对SAR ADC速度的影响,而且提高了高速动态锁存比较器电路的效率。仿真结果表明,在输入信号为25 MHz、采样频率51 MS/s的条件下进行仿真,该A/D转换器的功耗为0.61 m W,FOM值为89 f J/conv,信号噪声失真比(SNDR)为44.34 d B,无散杂动态范围(SFDR)为51.6 d B,有效位数(ENOB)为7.07 d B。在固定单位电容的结构中,只在差分结构两端最高位各增加一个寄存器资源的条件下,以增加0.05 m W的功耗代价,使速度相对于传统结构提高了一倍。In this paper, an 8-Bit 51 MS/s SAR-ADC in 180 nm CMOS Process is designed. With the improved structure of DAC, not only does the impact of the MSB capacitance on the speed of SAR ADC decreases, but also the efficiency of the high-speed clocked-comparator raised. The simulation results show that the SNDR of the ADC is 44.3 d B, the SFDR is 51.6 d B, and the ENOB is 7.07 d B at 25 MHz input signal frequency and 51 MHz sample clock frequency. The total power dissipation of this converter is 0.61 m W, and the FOM is 89 f J/conv with a 1.8 V supply. Based on fixed unit capacitance, the design in this paper doubles the speed compared to the original structure with only one more register and 0.05 m W more power consumption.

关 键 词：A/D转换器 高速 逐次逼近ADC 电容分裂 MSB电容减小 

分 类 号：TN402[电子电信—微电子学与固体电子学]