CAN总线控制器IP设计  

Design of CAN Bus Controller IP

作　　者：汪晓翔 马琪[1] WANG Xiaoxiang, MA Qi(CAD Research Center, Hangzhou Dianzi University, Hangzhou 310018, China)

机构地区：[1]杭州电子科技大学微电子CAD研究所,浙江杭州310018

出　　处：《电子科技》2018年第10期29-32,共4页Electronic Science and Technology

基　　金：国家自然科学基金青年基金(61404041)

摘　　要：CAN总线是面向工业测控系统通信应用的有效解决方案,文中提出一种高可靠性、高实时性和低成本的CAN总线控制器IP核设计方案。该IP核采用Verilog硬件描述语言,实现了CAN2. 0数据链路层协议,具备查错纠错能力,总线参数灵活可配满足不同应用需求。此外,将CAN总线控制器集成到片上系统,搭建完整FPGA验证平台,设计的CAN总线控制器作为CAN总线上的一个节点,验证该IP核的功能。实验结果表明,该CAN总线满足应用需求,控制器传输速率达到1 Mbit·s^(-1),传输报文丢失率低。The CAN bus was an efficient solution for real - time and high - speed communication in industrialapplication. This paper proposed a CAN bus controller IP core design with high reliability, high real - time and low -cost application. With the usage of Verilog, the logical link layer of CAN2.0 protocol was implemented by the IP corewhich was capable of error check and correcting. Besides, the CAN bus could be flexibly equipped to meet differentapplication needs. Additionally, the CAN bus controller was integrated into a system - on - chip and a FPGA platform was set up for function verification and performance estimation. As a node on the CAN bus, the CAN bus con-troller was responsible for the verification of the IP core function. The experiment result showed the transmission rateof the IP could achieve 1 Mbit · s-1 and the loss rate was very low.

关 键 词：CAN总线控制器 IP核 片上系统 FPGA验证 

分 类 号：TN47[电子电信—微电子学与固体电子学]