基于0.13μm SOI CMOS工艺的高性能LDO设计  

Design of high-performance LDO based on 0.13μm SOI CMOS process

作　　者：李雅淑[1] 高超嵩 孙向明[1] 杨苹 LI Ya-shu;GAO Chao-song;SUN Xiang-ming;YANC Ping(Silicon-Pixel Laboratory at Central China Normal University,Wuhan 430079,China)

机构地区：[1]华中师范大学像素实验室,湖北武汉430079

出　　处：《电子设计工程》2018年第19期165-170,共6页Electronic Design Engineering

基　　金：国家自然科学基金面上项目(11375073);国家自然青年科学基金(11605071)

摘　　要：基于电子设备对电源管理芯片的需求,本文设计了一种输出电压2.8 V,最大负载电流为50mA的高性能低压差线性稳压器(low-dropout regulator,LDO)。该LDO采用调整管栅极驱动技术,改善了负载瞬态响应,同时利用片外电容的等效串联电阻(Equivalent Series Resistance,ESR)补偿系统频率,保证了LDO的稳定性。在国产0.13μm Silicon-On-Insulation CMOS工艺上,实现了电路原理图和版图的设计,芯片面积(不包含PAD)为0.009 mm2。该LDO电路使用Cadence、Spectre等工具进行了仿真验证,仿真结果表明:输出电压为2.8 V,输出过冲小于8 mV,最大负载响应时间为2.1μs,相位裕度大于77°,低频时电源电压抑制比PSRR为-90 dB,负载调整率为53μV/mA,线性调整率为3.37 mV/V。Based on the requirement of electronic devices to power management chip, this paper presents a high performance low dropout linear regulator （LDO） with an output voltage of 2.8 V and a maximum source current of 50 mA. The LDO employs a tunable gate driving technology to improve its load transient response capability. Besides, the LDO adopts an ESR parasitic resistance generated by an off-chip capacitance to compensate its system frequency. Hence LDO can work stably. The schematic and layout of the LDO has been designed in a domestic 0.13μm silicon-on-insulator （SOl） CMOS process. The area without PADs is 0.009 mm^2. The simulations from Spectre tool show that the LDO has features of an output voltage of 2.8V, a response time of 2.1 μs with a maximum overshoot voltage of 8mV, a phase margin of larger than 77°, a power supply rejection ratio （PSRR） of-90dB at low frequency, a load regulation of 53 μV/mA and a linear regulation of 3.37 mV/V.

关 键 词：低压差线性稳压器 SOI工艺 高稳定性 瞬态响应 电源抑制比 

分 类 号：TN433[电子电信—微电子学与固体电子学]