一种应用于多通道模数转换器的串行输出接口设计  

A Serial Interface for Multi-channel ADC

作　　者：穆敏宏 叶凡[1] 任俊彦[1] MU Minhong;YE Fan;REN Junyan(State Key Laboratory of ASIC ＆ System,Fudan University,Shanghai 201203,China)

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2018年第5期596-604,共9页Journal of Fudan University：Natural Science

基　　金：国家高技术研究发展计划(2013AA014101)

摘　　要：本文设计了一款适用于高速多通道模数转换器的串行输出接口,包括扰码、并串转换、DLL与CML等模块,实现了3∶1并转串输出.相比于传统串行扰码发生器的结构,本文提出了一种新的并行扰码发生器设计方法,能缩短关键路径的延时.同时,文中还对串行输出接口进行了设计优化,降低了温度、电压波动带来的影响,面积、功耗等性能均有提升.串行输出接口采用65nm CMOS工艺设计,数字模块电路(扰码发生器、并串转换电路、DLL)的版图面积为72μm×97μm,CML输出电路的版图面积为85μm×53μm.版图后仿真显示单通道总功耗11.5mW,在不同输入相位下均能实现并行1.33Gb/s×3bits到串行4Gb/s×1bit的并串转换,满足模数转换器对输出接口的要求.A serial interface is designed for multi-channel Analog-to-Digital Converter（ADC）.This paper proposed a new method which can improve the speed of the scrambler greatly.The proposed serial interface compensates the influences caused by process,supply voltage and temperature,thus has an advantage in performance.The serial interface is designed in a 65 nm CMOS process.The digital circuit occupies an active area of 72μm×97μm and the CML occupies an active area of 85μm×53μm.The serial interface is able to convert 3-way 1.33 Gb/s parallel signal to 1-way 4 Gb/s serial signal with a power consumption of 11.5 mW,which meets the requirements of multi-channel ADC.

关 键 词：多通道模数转换器 串行输出接口 延迟锁定环 电流模逻辑 

分 类 号：TN402[电子电信—微电子学与固体电子学]