数字逻辑电路层次性虚拟仿真实验设计  

Hierarchical Virtual Simulation Experiment Design of Digital Logic Circuit

作　　者：廖小芳[1] LIAO Xiao-fang(Chengdu College of University of Electronic Science and Technology of China,Chengdu Sichuan 611731,China)

机构地区：[1]电子科技大学成都学院电子工程系,四川成都611731

出　　处：《科技视界》2018年第28期36-37,共2页Science & Technology Vision

摘　　要：结合应用型本科学生的特点,基于Multisim对数字逻辑电路的虚拟仿真实验进行层次性设计,通过层次性实验实施,加深学生对数字逻辑电路的理解,激发学习兴趣。Combined with the characteristics of applied undergraduate students,a series of hierarchical virtual simulation experiments of digital logic circuits are designed based on Mulfisim. Through the implementation of hierarchical experiments,students can have a deeper understanding of digital logic circuits and their interest in learning is stimulated.

关 键 词：MULTISIM 数字逻辑 仿真 

分 类 号：TN791[电子电信—电路与系统]