LV/HV N-Well BCD[B]技术(2)的芯片与制程剖面结构  

Structure of Chip and Process in LV/HV N-Well BCD[B] Method(2)

作　　者：潘桂忠 PAN Guizhong1,2(1. Shanghai Belling Co., Ltd, Shanghai 200233, China. 2. The 771 electronics technique institute of China Aerospace Science and Technology Research Academy, Shaanxi 710600, China.)

机构地区：[1]上海贝岭股份有限公司,上海200233 [2]中国航天电子技术研究院第七七一研究所,陕西710600

出　　处：《集成电路应用》2018年第11期31-35,共5页Application of IC

基　　金：上海市软件和集成电路产业发展专项基金(2009.090027)

摘　　要：LV/HV N-Well BCD[B]技术(2)能够实现MOS器件低压5 V与高压100～700 V (或更高)和双极型器件低压5 V与高压30～100 V兼容的BCD工艺。为了便于高低压器件兼容集成,采用源区为硼磷双扩散形成沟道的具有漂移区的偏置栅结构的HV LDMOS器件,并同时形成HV双极型器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到不同的高电压。采用芯片结构设计、工艺与制造技术,依该技术得到了芯片制程结构。LV/HV N-Well BCD [B] technology（2） can realize low-voltage 5 V and highvoltage 100～700 V（or higher） of MOS devices and low-voltage 5 V and high-voltage 30～100 V compatible BCD process of bipolar devices. In order to facilitate compatible integration of high and low voltage devices, HV LDMOS devices with bias gate structure of drift region were fabricated by double diffusion of boron and phosphorus in the source region. It forms HV bipolar devices simultaneously. Different high voltage can be obtained by changing the length, width, junction depth and doping concentration of the drift region. The technology of chip structure design, process and manufacturing technology is adopted.

关 键 词：集成电路制造 偏置栅结构 LV/HV N-Well BCD[B]技术 制程剖面结构 

分 类 号：TN405[电子电信—微电子学与固体电子学]