基于变压器耦合匹配的E波段低损耗二倍频器  

An E-band Low Loss Doubler Based on Transformer Coupling Matching

作　　者：王龙 文进才[1] 张青平 王永贺 吕佳梅 WANG Long;WEN Jincai;ZHANG Qingping;WANG Yonghe;LU Jiamei(Key Laboratory of RF Circuits and Systems,Ministry of Education,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2018年第6期6-11,共6页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：国家自然科学基金资助项目(61674047)

摘　　要：基于65nm CMOS工艺设计了一个低损耗的E波段二倍频器电路。采用单平衡对管结构并选取合适的偏置电压,电路可实现最优的二倍频输出,并有效抑制基波。同时,在单平衡对管输入端引入了一种叠层变压器耦合结构来实现低损耗、高效率的匹配,在保持极佳的幅度及相位平衡性的同时简化了输入偏置方式和版图布局。基于电磁场的全电路仿真结果显示,偏置电压为1.2V、输入功率为5dBm时,电路在67~93GHz频段能够实现-3dB到-6dB的转换增益,同时基波抑制大于25.6dB,芯片总面积为0.60mm×0.38mm。An E-band low loss doubler chip is presented in a 65 nm CMOS process in this paper.For enhancing the generation of second harmonic and the suppression of fundamental frequency,singlebalanced circuit topology and suitable bias voltage is adopted.In addition,a stacked transformer coupling structure is introduced at the input of the single-balanced geminate transistor to achieve low loss and high efficiency matching,which simplifies the input bias network and layout while maintaining excellent amplitude and phase balance.According to the whole circuit＇s electromagnetic field simulation results,proposed doubler has a conversion gain of-3 dB to-6 dB in the 67~93 GHz,with an input power of 5 dBm,under 1.2 VDC supply.Fundamental frequency suppression is better than 25.6 dB.The chip size including pads is 0.60 mm×0.38 mm.

关 键 词：二倍频器 E波段 低损耗 变压器耦合 

分 类 号：TN432[电子电信—微电子学与固体电子学]