USB2.0设备接口芯片从模式设计与实现  

Design and Implementation of Slave Mode of USB2.0 Device Interface Chip

作　　者：金君潇 王亚军[1] 赵琳娜 虞致国 魏敬和[2] 顾晓峰 

机构地区：[1]江南大学电子工程系轻工过程先进控制教育部重点实验室,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2015年第8期25-28 48,48,共5页Electronics & Packaging

基　　金：江苏省自然科学基金(BK20130156);中央高校基本科研业务费专项资金(JUSRP1026;JUSRP51323B);江苏省科技厅产学研联合创新资金(BY2013015-19);江苏省六大人才高峰资助项目(DZXX-027);江苏省普通高校研究生实践创新计划项目(SJZZ_0148);无锡市物联网发展资金项目(0414B011601140016PB)

摘　　要：为了使USB接口能适应多样化的外围设备,以USB高速设备接口芯片的SoC模型为基础,设计并实现了一种从属结构的数据传输模式,详细分析了从模式传输原理、端点工作机制、固件程序设计、仿真平台设计及仿真结果。以Verilog硬件描述语言设计了仿真平台,包括例化Design Ware库中的USB主机验证IP核作为数据发送接收的主机端,外部数据存储器作为外设数据的中转站,并通过比较主机端的发送和回读数据验证了设计的正确性。结果表明,外部控制器可控制处于从模式的USB设备接口芯片,实现数据在主机与设备之间的交互,此模式下能够有效地提高数据的传输速率,改善数据传输系统的工作效率。In order to make the USB interface meet the requirements of diverse peripheral equipments, a slave structure of data transmission mode based on the SoC model of high speed USB device interface chip is designed and implemented. The slave mode transmission principle, the endpoint working mechanism, the firmware design, the simulation platform design, and the simulation results are described in detail. The simulation platform is built by Verilog hardware description language, including using the host verification IP core from DesignWare library as the host end for data transmitting and receiving, and using the external data RAM as the transfer station for peripheral data. The correctness of design is verified by comparing the original data transmitted from the host end and the data read back. The results show that the slave mode of the USB device interface chip can be controlled by the external controller to realize data interaction between the host and the device, helping to increase the data transmission rate and improve the efficiency of data transmission systems.

关 键 词：USB 从模式 外部控制器 数据传输 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构]