浮点加法运算器前导1预判电路的实现  

The Design of Leading-One Prediction in Floating-Point Adder

作　　者：李笑盈[1] 孙富明[2] 夏宏[1] 

机构地区：[1]北京科技大学信息工程学院,北京100083 [2]国防科技大学电子工程学院,长沙410073

出　　处：《计算机工程与应用》2002年第21期142-143,146,共3页Computer Engineering and Applications

摘　　要：提出了一种应用于浮点加法器设计中前导1预判电路(LOP)的实现方案。此方案的提出是针对进行浮点加减运算时,尾数相减的结果可能会产生若干个头零,对于前导1的判断将直接影响规格化左移的位数而提出的。前导1的预判与尾数的减法运算并行执行,而不是对减法结果的判断,同时,并行检测预判中可能产生的1位误差,有效缩短了整个加法器的延时。LOP电路设计采用VHDL语言门级描述,已通过逻辑仿真验证,并在浮点加法器的设计中得到应用。A circuit design scheme is proposed in this paper,which implements the leading-one prediction(LOP)logic in floating-point addition.In the computation of floating-point addition,it might generate some leading zeros in the sub-traction of mantissa.The prediction of the leading-one directly affects the left shift bits for normalization.That is the purpose of our design.The prediction is not the justification of the result from the adder,but operating in parallel with subtraction.In addition,the paper presents the concurrent detection of possible one bit error in the prediction.It reduces the delay of the whole floating-point adder.The LOP circuit module is described in gate level with VHDL,which has passed the logic simulation and verification.It is applied to the design of floating-point adder.

关 键 词：浮点加法运算器 前导1预判电路 规格化 设计 逻辑仿真 

分 类 号：TP332.21[自动化与计算机技术—计算机系统结构]