一种基于混合仿真技术的电路并行后仿真加速算法  

A Hybrid Direct-Iterative Parallel Matrix Solving Algorithm for Post Layout Circuit Simulation

作　　者：刘伟平[1,2] 周振亚 蔡懿慈[1] Liu Weiping;Zhou Zhenya;Cai Yici(Department of Computer Science and Technology, Tsinghua University, Beijing 100084;Huada Empyrean Software Co., Ltd, Beijing 100102)

机构地区：[1]清华大学计算机科学与技术系,北京100084 [2]北京华大九天软件有限公司,北京100102

出　　处：《计算机辅助设计与图形学学报》2016年第11期2016-2020,共5页Journal of Computer-Aided Design & Computer Graphics

摘　　要：随着集成电路制造工艺的发展,芯片的特征尺寸不断地缩小,寄生电阻和电容对电路性能的影响也变得越来越显著,电路后仿真成为集成电路设计验证不可缺少的关键技术.但是集成电路规模的不断增大,寄生电阻和电容的数目急剧膨胀,电路后仿真中求解线性方程组所需要的时间急剧增加,导致电路验证时间越来越长,影响集成电路的设计周期和产品交付时间.文中利用超图划分的方法将电路划分成若干个相互耦合的子模块,子模块的矩阵求解应用LU分解方法,顶层矩阵求解利用GMRES方法;针对GMRES方法收敛速度慢的问题,根据快节点和电源网格节点本身的物理特性提出一种预处理算法,能够显著加速线性方程组的求解速度,从而提升电路的仿真效率.该算法已经应用到华大九天的电路仿真工具ALPS中,通过大量工业实际用例的测试,证明了算法的有效性.With the process node continually scaling down, circuit performance degradation becoming more andmore dramatic due to parasitic elements. Post layout circuit simulation is now an indispensable flow in analog/mixed signal design. But post layout circuit simulation usually increases tens even hundreds of times comparingwith pre-layout simulation because of the huge amount of parasitic elements. Matrix solving is the most timeconsuming part in post layout circuit simulation. This paper proposed a novel hybrid direct-iterative parallel methodwhich could significantly reduce matrix solving time. The proposed method used hyper graph partitiontechnology to partition the circuit into several coupling sub-circuits. LU decomposition and GMRES were used tosolve the corresponding internal and coupling equations. This paper then proposed an effective preconditionedGMRES method by utilizing the physical characteristics of fast nodes and power girds. The method had beensuccessfully implemented in Huada’s circuit simulator ALPS. The experimental results demonstrated the effectivenessof the proposed method.

关 键 词：集成电路 电路后仿真 寄生器件 线性方程组 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]