TP RAM的低功耗优化设计及应用  

Low power optimization of TP RAM and application

作　　者：周清军[1] 刘红侠[2] ZHOU Qingjun;LIU Hongxia(ZTE Telecom College, Xi’an Peihua University, Xi’an 710125, China;Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071, China)

机构地区：[1]西安培华学院中兴电信学院,西安710125 [2]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《计算机工程与应用》2017年第16期237-240,257,共5页Computer Engineering and Applications

基　　金：国家自然科学基金(No.61376099;No.6143000024);陕西省教育厅专项基金项目(No.16JK2138)

摘　　要：针对SoC中TP RAM的面积及功耗较大问题,提出一种优化设计方法。通过将SoC中的TP RAM替换成SP RAM,在SP RAM外围增加读写接口转换逻辑,使替换后的RAM实现原TP RAM的功能,保持对外接口不变。为了进一步降低功耗,使用自适应门控时钟,对地址总线进行格雷编码。将文中方法应用于一款多核SoC芯片,该芯片经TSMC 28 nm HPC工艺成功流片,die size为10.5 mm×11.3 mm,功耗为17.07 W。测试结果表明,优化后的RAM面积减少了25.2%,功耗降低了43.07%。As the area and power consumption of TP RAM in SoC are large,a new design method of optimization is proposed.In order to achieve the function of the original TP RAM and keep the external interface unchanged,TP RAM is replaced with SP RAM,and read-write interface logics of conversion are added around SP RAM.For less power,adaptive clock-gating is used and address bus is encoded through Gray code.The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC28nm HPC process.The chip occupies10.5mm×11.3mm of die area and consumes17.07W.The testing results indicate that the area of optimized RAMs is reduced by25.2%,and the power saving is43.07%.

关 键 词：伪双口随机存储器(TPRAM) 单口随机存储器(SPRAM) 接口转换逻辑 自适应门控时钟 格雷码 

分 类 号：TN402[电子电信—微电子学与固体电子学]