基于FPGA的图像超分辨率的硬件化实现  

FPGA-based hardware implementation of image super-resolution

作　　者：钟雪燕[1] 夏前亮[2] 陈智军[3] ZHONG Xueyan;XIA Qianliang;CHEN Zhijun(Nanjing Institute of Railway Technology,Nanjing 210031,China;CETC Deqing Huaying Electronics Co.,Ltd.,Huzhou 313200,China;Nanjing University of Aeronautics and Astronautics,Nanjing 211106,China)

机构地区：[1]南京铁道职业技术学院,江苏南京210031 [2]中电科技德清华莹电子有限公司,浙江湖州313200 [3]南京航空航天大学,江苏南京211106

出　　处：《现代电子技术》2017年第17期44-46,50,共4页Modern Electronics Technique

基　　金：国家自然科学基金面上项目(51475240);航空科学基金自由探索类项目(2014ZD52053);江苏省轨道交通控制工程技术研究开发中心开放基金(KFJ1509)

摘　　要：设计基于FPGA的图像超分辨率双线性插值实现方式,提出基于单输入双输出端口RAM缓冲的二级循环调度机制,用以实现共享资源分配和并行流水处理。单输入双输出端口的RAM实现读取相邻地址的两个数据,RAM的深度为源图像一行的像素点数,宽度为像素数据宽度,实现源数据相邻两行像素的存储。根据位置分析模块得到源图像的位置,将源图像的数据写入相应RAM中进行加权运算。为了提高效率使用乒乓算法,设计了4个RAM,2个RAM为一组,一组RAM在加权运算时,另一组RAM写入数据。该设计在Kintex-7开发板上得到验证,实现图像处理速度达到25~30 f/s,同时图像插值后不仅细节更加清晰,从直方图中可以看到图像得到了均衡化。An FPGA-based implementation mode of image super-resolution bilinear interpolation was designed.A two-stageround-robin scheduling mechanism based on RAM with single-input and dual-output port is proposed to realize the shared resource allocation and parallel pipeline processing.RAM with single-input and dual-output port can read two data whose address areadjacent.The quantity of pixels within a row in source image is deemed as the depth of RAM,and the width of pixel data isdeemed as that of RAM to store the two rows of pixels adjacent to the source data.The position of source image is gotten accordingto the position analysis module.The data of source image is written into the corresponding RAM for weighting operation.In orderto improve the efficiency,the ping-pong algorithm is adopted to design four RAMs which are divided into two groups(each oneincludes two RAMs).If one group of RAMs is performed with weighting calculation,another group of RAMs is performed withdata write-in.The design was verified on Kintex-7development board,which can process the image with the speed of25~30f/s.The interpolated image has clear detail.The image is equalized,which is shown in histogram.

关 键 词：FPGA 超分辨率 双线性插值 循环调度 

分 类 号：TN911.73-34[电子电信—通信与信息系统] TP391[电子电信—信息与通信工程]