一种提取纳米CMOS器件中源/漏寄生电阻的恒定迁移率方法  

A Constant-Mobility Method to Extract Source/Drain Parasitic Resistance for Nanometer CMOS Devices

作　　者：鲁明亮 陶永春[2] Lu Mingliang;Tao Yongchun(School of Rail Transportation,Nanjing Technical Vocational College,Nanjing 210019,China;School of Physics and Technology,Nanjing Normal University,Nanjing 210023,China)

机构地区：[1]南京高等职业技术学校轨道交通学院,江苏南京210019 [2]南京师范大学物理科学与技术学院,江苏南京210023

出　　处：《南京师大学报（自然科学版）》2018年第1期50-54,60,共6页Journal of Nanjing Normal University(Natural Science Edition)

基　　金：国家自然科学基金(10947005)

摘　　要：源/漏寄生电阻作为器件总电阻的一个重要组成部分,严重制约着纳米CMOS器件性能.随着纳米CMOS器件尺寸不断减小,源/漏寄生电阻占器件总电阻比例越来越高,已经成为衡量CMOS器件可靠性的一个重要参数.本文提出一种恒定沟道迁移率条件下提取纳米CMOS器件中源/漏寄生电阻的方法.本方法通过测量固定偏压条件下一个器件的两条线性区I_d-V_(gs)曲线之比,推导出纳米CMOS器件中源/漏寄生电阻,操作简单,精确度高,避免了推导过程中由沟道迁移率退化引入与器件栅长相关的误差.我们详细研究并选取合适外加偏压条件,保持推导过程中沟道迁移率恒定,确保源/漏寄生电阻值的稳定性.在固定外加偏压条件下,我们提取了45 nm CMOS工艺节点下不同栅长器件的源/漏寄生电阻值,结果表明源/漏寄生电阻值与栅长不存在直接的依赖关系.最后,我们研究了工艺过程和计算过程引入的波动并进行了必要的误差分析.As a significant fraction of the total device resistance,source/drain parasitic resistance seriously limits the performance of deeply nanometer CMOS devices.The source/drain parasitic resistance is becoming a larger fraction of the total device resistance as the nanometer CMOS scales down.Therefore,it is a important parameter of reliability for CMOS devices.A source/drain parasitic resistance extraction method is proposed from the conditions in which the channel mobility remains constant.Source/drain parasitic resistance is extracted from the ratio of two linear I d-V gs curves in the fixed bias conditions.This method avoiding the gate length dependent errors induced by mobility degradation in extraction procedures is simple and accurate.We specifically arrange the bias conditions in which the effect of vertical electrical filed on channel mobility is eliminated and the stability of the source/drain parasitic resistance is ensured.Under the suitable bias conditions,the source/drain parasitic resistances of different gate length under 45 nm technology is extracted,and it is independent with the gate length.Finally,the fluctuations of process and calculation are investigated and the errors are analyzed.

关 键 词：纳米CMOS器件 源/漏寄生电阻 提取方法 

分 类 号：TN386.1[电子电信—物理电子学]