一种基于FPGA的低功耗高速解码器设计  

A low power and high speed decoder design based on FPGA

作　　者：周松江 李圣辰 刘明 Zhou Songjiang;Li Shengchen;Liu Ming(Institute of Information Photonics and Optical Communications,Beijing University of Posts and Telecommunications,Beijing 100876)

机构地区：[1]北京邮电大学信息光子学与光通信研究院,北京100876

出　　处：《电子技术应用》2018年第4期27-32,共6页Application of Electronic Technique

摘　　要：针对传统编解码算法复杂度高、不易扩展等问题,对自编码神经网络前向传播算法和结构进行了研究,提出了一种以自编码神经网络为编解码算法,以FPGA为实现平台的低功耗高速解码器系统。该系统实现了字符的编解码,同时可被应用于各种多媒体信息的编解码。通过Model Sim仿真,Xilinx ISE实现后进行硬件实测,对计算精度、资源消耗、计算速度和功耗等进行分析。实验测试结果表明,所设计的解码器能够正确完成数据解码功能,算法简洁高效,扩展能力强,系统具有低功耗、速度快等特点,可广泛应用于各种低功耗、便携式产品。In view of the complexity and inflexibility of the traditional encoding and decoding algorithms,this paper studies the forward propagation algorithm and structure of autoencoder neural networks.A low power consumption and high speed decoder system is proposed,using the autoencoder neural network as the codec algorithm with FPGA implementation.The system realizes the decoding of characters,and can be applied to the decoding of various multimedia information.Through ModelSim simulation and Xilinx ISE implementation,the hardware measurement are carried out,and the calculation accuracy,resource consumption,calculation speed and power consumption are analyzed.Experimental results show that the designed decoder can decode data correctly,the algorithm is efficient,scalable,the proposed system has the characteristics of low power consumption and high speed,and it can be widely used in a variety of low power,portable products.

关 键 词：FPGA 解码器 自编码神经网络 硬件实现 高速低功耗 

分 类 号：TN791[电子电信—电路与系统] TP183[自动化与计算机技术—控制理论与控制工程]