一种适用于DDR内存驱动的LDO芯片设计  

A Design of LDO Chip for DDR Memory Driver

作　　者：蔡胜凯 王卓[1] 马亚东[1] 汪尧 明鑫[1] 张波[1] CAI Shengkai;WANG Zhuo;MA Yadong;WANG Yao;MING Xin;ZHANG Bo(Power Integrated Technology Laboratory of UESTC,Chengdu 610000,China)

机构地区：[1]电子科技大学功率集成实验室,成都610000

出　　处：《电子与封装》2018年第4期13-17,共5页Electronics & Packaging

摘　　要：介绍了一种适用于DDR内存驱动的LDO芯片。采用跨导线性环结构增大摆率,具有快速的瞬态响应。控制环路上下通道不匹配,采用单边米勒补偿方式,形成环路主极点和零点,再引入电阻R3形成补偿零点,环路整体表示为单极点系统,具有很好的稳定性。该LDO的典型输入电压为1.2 V,输出电压为0.6 V,负载电容为10μF,具有1.5 A的电流抽取和灌出能力,同时集成了2.6 A的电流限功能,满足了DDR内存的应用需求。采用0.35μm BCD工艺进行仿真验证,仿真结果表明该设计具有很好的瞬态调整能力和稳定性。In the paper,a design of LDO chip for DDR memory driver is described.The LDO uses translinear loop structure to increase the slew rate,making the LDO has a fast transient response.The upper and lower channels of the control loop do not match each other.One-sided Miller compensation is used to form the main pole and zero of the loop.Then the resistor R3 is introduced to form the compensation zero.The loop is represented as a single-pole system with good stability.The typical input voltage of the LDO is 1.2 V,the output voltage is 0.6 V,the load capacitance is 10μF,with 1.5 A current sinking and sourcing ability,while integrating the 2.6 A current limit ability.This design meets the DDR memory application needs.The design is simulated by using 0.35μm BCD process.The simulation results show that the design has good transient adjustment ability and stability.

关 键 词：DDR内存驱动 跨导线性环 快速瞬态响应 

分 类 号：TN402[电子电信—微电子学与固体电子学]