一种数字锁相环的FPGA实现  

A kind of Digital PLL and Their FPGA Implementation

作　　者：李荃 项顺祥[1] 黄麟舒[1] LI Quan;XIANG Shun-xiang;HUANG Lin-shu(College of Electronic Engineering,Naval University of Engineering,Wuhan Hubei 430033)

机构地区：[1]海军工程大学电子工程学院,湖北武汉430033

出　　处：《数字技术与应用》2018年第2期83-84,共2页Digital Technology & Application

摘　　要：本文介绍了一种数字锁相环的FPGA实现,简单介绍了锁相环的基本原理,并对每一模块的FPGA实现的设计进行了介绍,最后通过仿真验证了其性能。This paper introduces a FPGA implementation of digital phase-locked loop,introduces the basic principle of PLL,and introduces the design of FPGA implementation for each module.Finally,its performance is verified by simulation.

关 键 词：数字锁相环 FPGA MODELSIM 

分 类 号：TM764[电气工程—电力系统及自动化]