基于新型结构的小面积全数字DDR接口模块  

A Small Area All Digital DDR PHY Based on a Novel Structure

作　　者：陈宇轩 梁利平 CHEN Yuxuan;LIANG Liping(Institute of Microelectronics,University of Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]中国科学院大学微电子研究所,北京100029

出　　处：《湖南大学学报（自然科学版）》2018年第4期155-160,共6页Journal of Hunan University:Natural Sciences

基　　金：国家自然科学基金资助项目(2013ZX03003015)~~

摘　　要：提出一种新型全数字鉴相器结构.该结构消除了亚稳态影,并通过采用特殊的延迟链结构,大大减少了模块的面积.将此结构应用于一款65nm low leakage工艺下工作频率在100~400MHz的全数字DDR接口模块,总面积4 298μm2,DLL面积2 350μm2.芯片的测试结果验证了设计的准确性,与传统的结构相比本模块面积较小,且由于其全数字电路的特点具有较好的可移植性.This paper proposed a novel phase detector structure that prevent the effect of metastability,and using a inverted delay line structure to reduce its area.The structure was implemented in SMIC 65 nm low leakage tech node inside an all digital DDR PHY which can work in frequency from 100~400 MHz.The total area is 4 298μm 2 and the DLL has a area of 2 350μm 2,chip testing results shows the IP works as expected.And since its all digital,the design also has good transplantability.

关 键 词：物理层 鉴相器 延迟锁定环 延迟链 面积 版图 

分 类 号：TN495[电子电信—微电子学与固体电子学]