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作 者:徐敏伟 刘光祖[1] 王建新[1] 潘炜程 XU Minwei;LIU Guangzu;WANG Jianxin;PAN Weicheng(School of Electronic and Optical Engineering,Nanjing University of Science and Technology,Nanjing 210094,China)
机构地区:[1]南京理工大学电子工程与光电技术学院,江苏南京210094
出 处:《探测与控制学报》2018年第2期83-87,92,共6页Journal of Detection & Control
摘 要:针对现有双二进制Turbo码译码器对预译码所得信息利用率低的问题,提出了基于预译码技术的Turbo码译码方法。该方法将预译码所得的后验似然比转换为后验概率并作为正式译码的先验概率。仿真结果表明,该方法可以提升0.3dB的译码性能,并且译码时延以及资源消耗和改进前保持一致。为了降低FPGA实现的复杂度,分支度量矩阵采用查找表的方式生成,在时钟频率为38.4MHz的情况下,一次译码迭代为5ms左右。In view of the low utilization ratio of the Du-binary Turbo codes decoder for the predecoding information,a method was proposed to improve the performance of the decoder by using the information obtained from the pre decoder.In this method,the posterior likelihood ratio of the predecoding was converted to the prior probability of the formal decoding.This method could improve the decoding performance of 0.3 dB,and the decoding time delay and resource consumption were consistent with the former methods.The branch metric matrix was generated by look-up table,which reduced the complexity of FPGA implementation,and one iteration of the decoding was about 5 ms,the FPGA clock frequency was 38.4 MHz.
关 键 词:双二进制Turbo码 预译码 后验似然比 先验概率 FPGA实现
分 类 号:TN911[电子电信—通信与信息系统]
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