面向PCIE 3.0总线的扰频和去扰频器FPGA设计  

FPGA-based designs of scrambler and descrambler for PCI Express 3.0 bus

作　　者：陆启立 黄新明 孙玲[1,2] 谢星 韩赛飞 唐天泽 LU Qili;HUANG Xinming;SUN Ling;XIE Xing;HAN Saifei;TANG Tianze(School of Electronic Information,Nantong University,Nantong 226019,China;Jiangsu Key Laboratory of ASIC Design,Nantong 226019,China)

机构地区：[1]南通大学电子信息学院,江苏南通226019 [2]江苏省专用集成电路设计重点实验室,江苏南通226019

出　　处：《现代电子技术》2018年第16期47-50,54,共5页Modern Electronics Technique

基　　金：国家自然科学基金项目(61571246)~~

摘　　要：在分析PCI Express 3.0总线物理层协议的基础上,提出一种实现扰频器和去扰频器的设计方案。利用可综合Verilog HDL语言在Vivado平台下完成电路的设计综合并下载到FPGA开发板进行测试与验证。验证结果表明,设计满足PCI Express 3.0总线物理层的要求,占用逻辑资源少,可应用到总线物理层的总体设计中。A design scheme for implementation of the scrambler and descrambler is proposed on the basis of analyzing the physical layer protocol of the PCI Express 3.0 bus.The design synthesis of the circuit is accomplished on the Vivado platform by using the synthesizable Verilog HDL language,and downloaded to the FPGA development board for testing and verification.The verification results show that the design can meet the physical layer requirement of the PCI Express 3.0 bus,occupies little logic resources,and can be applied in the overall design for the physical layer of the bus.

关 键 词：PCI EXPRESS 3.0总线 扰频器 去扰频器 现场可编程门阵列 VIVADO 逻辑资源 

分 类 号：TN915.04-34[电子电信—通信与信息系统] TP336[电子电信—信息与通信工程]