7nm工艺下片上电感耦合情况研究  

Study on On-Chip Inductor Coupling Based on 7nm Process

作　　者：吴双 高博[1] 龚敏[1] WU Shuang;GAO Bo;GONG Min(Sichuan Key Lab.of Microelectronics Technology,Division of Microelectronics,College of Physical Science and Technology,Sichuan University,Chengdu 610064,China)

机构地区：[1]四川大学物理科学与技术学院微电子系,微电子技术四川省重点实验室,成都610064

出　　处：《电子与封装》2018年第8期17-22,共6页Electronics & Packaging

摘　　要：基于TSMC N7工艺,使用了Cadence公司的Virtuoso和Lorentz Solution公司的Peak View作为仿真与验证平台,在不同的电磁屏蔽条件下,对制作在最上两层金属上的两个相互之间距离变化的片上电感的耦合情况进行了研究。通过二者电感值的改变,分析了其耦合关系,以丰富射频器件模型。This paper is based on the TSMC N7 process,using Cadence's Virtuoso and Lorentz Solution's PeakView as simulation and verification platforms.We research on the coupling relationship between two on-chip inductors with different distances to each other on the top two layers of metal under different electromagnetic shielding conditions,and then analyzed the coupling relationship frominductance value of this two on-chip inductor.

关 键 词：片上电感 guardring GROUND SHIELDING 耦合 品质因数 

分 类 号：TM55[电气工程—电器]