基于Artix-7 FPGA的异步高速串行通信IP设计  

Design of an asynchronous high-speed serial communication IP core based on Artix-7 FPGA

作　　者：王蕾[1] 韩立峰[1] WANG Lei;HAN Lifeng(Laboratory of Aviation Cluster Technology and Operational Application,College of Air Traffic Control and Navigation,Air Force Engineering University,Xi’an 710051,China)

机构地区：[1]空军工程大学空管领航学院航空集群技术与作战运用实验室,陕西西安710051

出　　处：《现代电子技术》2018年第19期6-10,共5页Modern Electronics Technique

基　　金：陕西省电子信息系统综合集成重点实验室基金资助~~

摘　　要：设计一种基于Artix-7 FPGA的异步高速串行通信IP核,包含协议解析和抗干扰设计、跨时钟域缓冲区设计、用户接口和物理层接口设计,实现最小硬件系统。该IP核可结合高速串口驱动芯片简单对接至主流处理器,如DSP,ARM,PowerPC等,以扩展处理器的异步串行通信接口数量和通信速率。其中,通信速率最高可至30 Mb/s,扩展数量视FPGA内部资源而定,理论上无上限。在机载和地面设备中可广泛应用。An asynchronous high-speed serial communication IP core based on Artix-7 FPGA was designed,for which the protocol analysis,anti-jamming capability,clock crossing domain buffer,user interface and physical layer interface are designed to realize the minimum hardware system.The IP core combined with high-speed serial driving chip can simply connect to the mainstream processors such as DSP,ARM and PowerPC to increase the extension quantity of asynchronous serial communication interface and improve the communication rate.The maximum communication rate can reach up to 30 Mb/s,and the extension quantity is determined by the internal resource of FPGA and has no upper limit theoretically.This IP core can be widely used in airborne and ground equipments.

关 键 词：高速率通信 异步串行通信 DSP ARM Artix-7 处理器 

分 类 号：TN919.6-34[电子电信—通信与信息系统]