基于FPGA快速中值滤波算法的硬件实现  

Hardware Implementation of Fast Median Filtering Algorithm Based on FPGA

作　　者：赵亮 刘鹏[1] 王晓曼[1] 刘美 ZHAO Liang;LIU Peng;WANG Xiaoman;LIU Mei(School of Electronics and Information Engineering,Changchun University of Science and Technology,Changchun 130022)

机构地区：[1]长春理工大学电子信息工程学院,长春130022

出　　处：《长春理工大学学报（自然科学版）》2018年第5期97-100,115,共5页Journal of Changchun University of Science and Technology(Natural Science Edition)

摘　　要：针对传统中值滤波排序量多、速度慢的缺点,充分利用FPGA并行性的特点,采用以资源换取速度的思路,提出了一种基于FPGA的改进中值滤波算法。通过2个FIFO和7个寄存器可以形成包含9个像素的3x3移动窗口。窗口中的每一个数据独立运算,每一个数据均有两个变量,小于该数的个数以及等于该数的个数。结合中值在有序序列中处于中间位置这一特殊性判断该值是否为中值。独立运算的优势在于彼此间的计算互不关联,根据每个数据的两个变量值判断该值是否为中值。实验结果表明:该算法将计算中值的时钟周期数降至1个,从而达到了快速抑制噪声的目的。该设计对于实时图像预处理具有一定的工程参考及应用价值。Aiming at the defects of traditional median filter algorithm that has numerous sorting and slow speeds,taking full advantage of the parallelism of FPGA,in this paper,an improved median filter algorithm based on FPGA is proposed by adopting the resource exchanging speed.A 3x3 moving window with 9 pixels can be formed with 2 FIFOs and 7 registers.Each data in the 3x3 window is independent operation and each data has two variables,which the number is less than the data and the number is equal to the data.Combined with the particularity that the median is in the middle position in the ordered sequence,it is judged whether the value is the median.The experimental results show that the number of clock cycles to one cycle is reduced by the algorithm,and the purpose of fast noise suppression is achieved.The design of real-time image preprocessing has some engineering reference and application value.

关 键 词：有序序列 中值滤波 FPGA 图像预处理 

分 类 号：TN957.52[电子电信—信号与信息处理]