采用S-Tag的M-DSP片上存储DMA访问优化  

S-Tag based DMA optimization for on-chip memory in M-DSP

作　　者：鲁建壮[1] 孙书为[1] 陈胜刚[1] 陆文远 LU Jianzhuang;SUN Shuwei;CHEN Shenggang;LU Wenyuan(College of Computer,National University of Defense Technology,Changsha 410073,China;Xi′an Satellite Control Center,Xi′an 710043,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]西安卫星测控中心,陕西西安710043

出　　处：《国防科技大学学报》2018年第6期112-117,共6页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(61402499;61402500;61602493)

摘　　要：针对自主设计的M-DSP,提出并设计实现了一种基于Tag副本(S-Tag)的片上SRAM DMA访问数据相关性维护机制,该机制以流水化方式实现,在基本对CPU无打扰的前提下,有效支撑了DMA数据的无阻塞传递。仿真和芯片实测结果表明,该机制硬件开销较小,并在有效带宽和带宽利用率上均优于已有典型同类芯片。The S-Tag (Shadow Tag) mechanism of SRAM (static random access memory) data consistency maintaining for DMA (direct memory access) accessing was proposed for the independent design of M-DSP (multi-core digital signal processor). The pipelining implementation can efficiently support DMA non-blocking data transfer,and release the CPU. Experimental results and tests in real chips show that the proposed mechanism outperforms the state-of-art ones with respect to bandwidth and bandwidth utilization while keeping relatively lower hardware cost.

关 键 词：Cache+RAM结构 S-Tag DMA传输 数据一致性 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]