基于FPGA实现JESD204B高速接口设计  

Design of JESD204B high speed interface based on FPGA

作　　者：曹鹏飞 Cao Pengfei(Faculty of Intelligent Manufacturing,Tianjin Sino-German University of Applied Sciences,Tianjin 300350,China)

机构地区：[1]天津中德应用技术大学智能制造学院,天津300350

出　　处：《无线互联科技》2018年第23期19-21,共3页Wireless Internet Technology

基　　金：天津市科技计划项目-天津市科学普及项目;项目编号:18JCTPJC51200;天津中德应用技术大学科技培育一般项目;项目编号:zdkt2017-012

摘　　要：JESD204B接口是高速ADC和DAC芯片采用的数据通信接口之一,具有传输速率高,抗干扰能力强,芯片间同步方便等优点。目前国内JESD204B接口应用多由国外集成芯片提供,缺乏自主性和灵活性。为了加强JESD204B接口自主设计,文章阐述了基于FPGA GTX高速收发器实现JESD204B接口通信的方法,详细说明了JESD204B接口的FPGA设计实现方案、同步化处理机制等内容。利用多通道JESD204B接口实现高速串行数据的传输,有效解决了传统并行数据采集存在的问题,满足实际工程的应用需求。JESD204B interface is one of the data communication interfaces used by high-speed ADC and DAC chips. It has the advantages of high transmission rate, strong anti-interference ability and convenient synchronization between chips. At present, the application of JESD204 B interface in China is mostly provided by foreign integrated chips, lacking autonomy and flexibility. In order to strengthen the self-design of JESD204 B interface, this paper describes the method of realizing JESD204 B interface communication based on the GTX high-speed transceiver of FPGA, and describes in detail the implementation scheme of JESD204 B interface based on the FPGA, synchronization processing mechanism and so on. Using multi-channel JESD204 B interface to achieve high-speed serial data transmission, effectively solve the problems of traditional parallel data acquisition, and meet the application requirements of practical projects.

关 键 词：JESD204B FPGA 高速串行传输 数据采集 

分 类 号：TN792[电子电信—电路与系统]