一种高性能的全数字锁相环设计方案  

Design scheme for an all-digital phase locked loop with a high performance

作　　者：屈八一[1] 程腾[1] 俞东松 李智奇[2] 周渭[2] 李珊珊[1] 刘立东[1] QU Bayi;CHENG Teng;YU Dongsong;LI Zhiqi;ZHOU Wei;LI Shanshan;LIU Lidong(School of Information Engineering,Chang'an University,Xi'an 710064;School of Mechano-electronic Engineering,Xidian Univ.,Xi'an 710071,China)

机构地区：[1]长安大学信息工程学院,陕西西安710064 [2]西安电子科技大学机电工程学院,陕西西安710071

出　　处：《西安电子科技大学学报》2019年第1期112-116,共5页Journal of Xidian University

基　　金：国家自然科学基金(11773022;11873039;61701043);中央高校基本科研业务费专项资金(301824171002);长安大学大学生创新创业训练计划(201810710050)

摘　　要：针对实现参考频率和输出的频率近似相等或者近似成整数倍关系时遇到的锁相环设计方案复杂以及高性能的模拟锁相环不适宜于集成化问题,设计了主要由模数转换器、全数字式鉴相器、数字式低通滤波器和数控振荡器等构成的全数字式锁相环。主要利用模数转换器在动态量采集时具有的边沿效应从其采集的大量数据中选择出精度更高的数据用于后级的全数字式鉴相,实现了一种全数字式锁相环。实验结果表明了该方案的正确性及其具有锁定精度高和环路的本底噪声低等特性。Aiming at the fact that a complex scheme is needed when the two frequencies in the phase locked loop are close to each other or have an approximate integer multiple relationship and the traditional analog phase locked loop is unsuitable for integration and on chip implementation,an all-digital phase locked loop is proposed,which is mainly composed of analog to digital converters,an all-digital phase detector,a digital low pass filter and a digitally controlled oscillator.The analog to digital converters quantization errors have been greatly suppressed by using the clock cursor effect and digital edge effect and an all-digital phase locked loop with a high performance is achieved.Experiment indicates the correctness of the design scheme and shows that the proposed loop has characteristics of high precision and low noise.

关 键 词：数字锁相环 边沿效应 全数字式鉴相器 数控振荡器 

分 类 号：TN911.8[电子电信—通信与信息系统]